® An Introduction to the Intel QuickPath Interconnect

® 
An Introduction to the Intel 
QuickPath Interconnect

® An Introduction to the Intel QuickPath Interconnect

January 2009 Document Number: 320412-001US Notice: This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information. Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR ...IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Products which implement the Intel® QuickPath Interconnect may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Any code names presented in this document are only for use by Intel to identify products, technologies, or services in development, that have not been made commercially available to the public, i.e., announced, launched or shipped. They are not "commercial" names for products or services and are not intended to function as trademarks. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Core, Pentium Pro, Xeon, Intel Interconnect BIST (Intel BIST), and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. All Rights Reserved. 2 ® An Introduction to the Intel QuickPath Interconnect Contents Executive Overview ..............................................................................................................5 Introduction ........................................................................................................................5 Paper Scope and Organization ...............................................................................................6 Evolution of Processor Interface .............................................................................................6 Interconnect Overview ..........................................................................................................8 Interconnect Details ............................................................................................................10 Physical Layer ................................................................................................................... 10 Link Layer ......................................................................................................................... 12 Routing Layer .................................................................................................................... 14 Transport Layer ................................................................................................................. 14 Protocol Layer ................................................................................................................... 15 Performance ...................................................................................................................... 19 Reliability, Availability, and Serviceability ............................................................................... 21 Processor Bus Applications .................................................................................................. 21 Summary .......................................................................................................................... 22 ® An Introduction to the Intel QuickPath Interconnect 3 Revision History Document Number 320412 Revision Number -001US Initial Release Description § Date Read the full ® An Introduction to the Intel QuickPath Interconnect.

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