JESD204B Intel® FPGA IP

Intel provides the JESD204B serial interface in the industry across multiple products –from low-cost or low-power to high-performance FPGAs and SoCs. The JESD204B Intel® FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices.

Read the F-Tile JESD204B Intel® FPGA IP user guide ›

Read the F-Tile JESD204B Intel® FPGA IP design example user guide ›

Read the JESD204B Intel® FPGA IP user guide ›

Read the JESD204B IP Core design example user guide ›

Watch the JESD204B IP quick start video ›

JESD204B Intel® FPGA IP

The JESD204B Intel® FPGA IP incorporates:

  • Media access control (MAC)—data link layer (DLL) block that controls the link states and character replacement.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

With our unique implementation of a full transport layer, design engineers no longer need to analyze documentation to integrate or develop a transport layer solution. Intel’s hardware interoperability testing of the JESD204B Intel® FPGA Intellectual Property (IP) core with analog-to-digital converter (ADC) and digital-to-analog converter (DAC) vendors, RFICs, and analog front ends also gets you to market faster.

Features

The JESD204B Intel® FPGA IP core delivers the following key features:

  • Lane rates of up to 12.5 Gbps (characterized and certified to the JESD204B standard), and lane rates up to 19 Gbps for Intel Agilex® 7 E-tile, and up to 20 Gbps for Intel Agilex® 7 F-tile (uncharacterized and not certified to the JESD204B standard).
  • Runtime reconfiguration of JESD parameters (L, M, F, S, N, K, CS, CF, data rate).
  • Base and PHY partitioning for portability.
  • Subclass 0 operating mode for backward compatibility to JESD204A.
  • Subclass 1 and 2 operating modes for deterministic latency support between the ADC/DAC and FPGA.
  • Multidevice synchronization.
  • Serial lane alignment and monitoring.
  • Ability to tune latency in IP core.
  • Transceiver channel sharing for transmitter (TX) and receiver (RX) to optimize transceiver count.
  • Hardware-validated design examples that include transport layer design.

IP Status

 

Ordering Status

Production

Ordering Codes

Intel® FPGA IP JESD204 SUITE

IPS-JESD204 (contains JESD204B, JESD204B-FTILE, JESD204C, JESD204C-FTILE)
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Note: Texas Instruments' TSW14J57 and TSW14J56 evaluation modules (EVMs) are designed using Intel® Arria® 10 FPGAs and Arria® V FPGAs respectively. All devices from Texas Instruments supported by the TSW14J57EVM and the TSW14J56EVM have been hardware validated to be compatible with the JESD204B Intel® FPGA IP.

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† Tests measure performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase. For more complete information about performance and benchmark results, visit www.intel.com/benchmarks.

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