Nios® II Processors

Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios® II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and applications processing needs. The Nios® II processor supports all Intel® FPGA and SoC families.

Family Variants

What's New

See what's new with the Nios® II Processor and Nios II Embedded Design Suite.

Processor Performance

DMIPS (Dhrystones 2.1 benchmark) at Fmax by Device

Devices Nios® II /e
Economy
Nios® II /f
Fast
Cyclone® IV GX 
DMIPS at MHz (Dhrystones 2.1 benchmark)

30 at
175 MHz

190 at
165 MHz
Cyclone V GX 
DMIPS at MHz (Dhrystones 2.1 benchmark)

33 at

220 MHz

192 at

170 MHz

Arria® V GX 
DMIPS at MHz (Dhrystones 2.1 benchmark)

37.5 at

250MHz

226 at

200 MHz

Intel Arria I0 GX 
DMIPS at MHz (Dhrystones 2.1 benchmark)

52.5 at

350 MHz

305 at

270MHz

Stratix® V 
(DMIPS at MHz (Dhrystones 2.1 benchmark)
54 at
420 MHz
385 at
350 MHz

Benefits

Features

Design Tools

The Nios® II Embedded Design Suite (EDS) is a comprehensive development package for Nios® II software design.

Applications

Application

Nios II
Processor Core

 

Vendor

 

Description

Power and cost sensitive Nios II economy core Intel With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.
Real time Nios II fast core Intel

Absolutely deterministic, jitter free real-time performance with unique hardware real-time feature options

  • Vector Interrupt Controller
  • Tightly Coupled Memory
  • Custom instructions
    (ability to use FPGA hardware to accelerate a function)
  • Supported by industry-leading real-time operating systems (RTOS)
  • Nios II processor is the ideal real-time processor to use with DSP Builder-based hardware accelerators to provide deterministic, high performance real-time results
Applications processing Nios II fast core Intel With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux* operating system. Both open source and commercially supported versions of Linux for Nios II processors are available.

Intel FPGA Embedded Alliance

Application Nios II Processor Core Vendor Description
Safety critical Nios II SC core HCell Certify your design for DO-254 compliance by using the Nios II safety critical procesor core along with the DO-254 compliance design services offered by HCell.

Lockstep

Dual Core

Lockstep Solution Intel Utilize the flexibility of the Nios II processor and Intel's lockstep technology to provide systems with high diagnostic coverage, self-checking and advanced diagnostic features in full compliance with functional safety standards IEC 61508 and ISO 26262.

Ecosystem

Embedded IP Suite

Nios® II Processor

To obtain a new time-unlimited license file for the Nios II processor, you must purchase a standalone Nios II processor IP core license (ordering code: IP-NIOS). To renew your license, obtain a one-year renewal license (ordering code: IPR-NIOS). You can also purchase a value bundle that contains licenses for commonly used embedded IP cores—Embedded IP Suite (ordering code: IPS-EMBEDDED). Contact your local Intel representative or use the contact information on the Intel® software sales support page to order today. See Table 1 for ordering information.

Embedded IP Suite

The Embedded IP Suite is a value bundle of Intel's most popular embedded IP cores and software. This Embedded IP Suite contains all the building blocks for your embedded design, including the Nios II processor, DDR/DDR2/DDR3 memory controllers, a 16550 compatible UART, and a complete Ethernet solution with the Intel® FPGA IP for Triple-Speed Ethernet. The Embedded IP Suite is priced at $995. If purchased separately, the value of the cores and software add up to over $3,500. Contact your local Intel representative or use the contact information on the Intel® software sales support page to order today.


To obtain the latest updates, features, bug fixes, or technical services through mySupport for the Nios® II processor, your licenses must be current. Use the following information to select the intellectual property (IP) core license that best meets your requirements.

Getting started

Start your design today with the Nios II processor by purchasing one of the many low-cost evaluation or development kits available for the Nios II processor.

To ship designs featuring the Nios II processor, you will need to purchase a license for the Nios II processor.

Frequently Asked Questions

Frequently asked questions about the Nios II Processor.

The Nios II embedded processor family is Altera’s second-generation soft embedded processor solution. The Nios II processor cores are 32 bit RISC processors that share a common instruction set architecture and are optimized for use in all of Altera's mainstream FPGA families. Visit the Nios II processor page for details.

The Nios II processor is made available as three distinct cores to provide you with maximum design flexibility while balancing system performance needs and logic element (LE) usage. All three cores are included in the Nios II development kits and are supported by the SOPC Builder design tool.

 

The Nios II processor family is made up of these cores:

Nios II/f (fast)–Highest performance, moderate FPGA utilization

Nios II/s (standard)–High performance, low FPGA utilization

Nios II/e (economy)–Modest performance, lowest FPGA utilization

By implementing a processor as a hardware description language (HDL)-coded intellectual property (IP) core, you get an exact-fit solution because you can choose the peripheral, performance, and processor mix that best suits your system needs. Hard macro implementations are essentially ASICs and do not have the same flexibility; they take so long to deploy that you can't benefit from the latest process technology. Soft core processors, on the other hand, can migrate immediately to the latest FPGA technology such as the Stratix® or Cyclone FPGA series. Also, standard microprocessor-based solutions are subject to obsolescence issues, whereas Nios II-based solutions resist obsolescence because they are constructed from re-targetable HDL.

The Nios II processor has a 32 bit RISC instruction-set architecture, whereas the first-generation Nios processor has a 16 bit instruction-set architecture. The Nios II processor reaches new levels of efficiency and performance over the Nios processor core because it consumes much fewer FPGA resources yet quadruples computational performance. The Nios II processor also simplifies the processor selection process by providing a set of pre-optimized cores targeting specific price (logic usage) and performance constraints.

The Nios II processor family can be used in a wide range of applications that require a general-purpose, 32 bit embedded microprocessor.

The Nios II processors are fully supported by all Altera SoC, FPGAs, and HardCopy ASICs.

The Nios II processor IP license is royalty-free, and perpetual which means it allows user to use the Nios II processor IP core forever and has no limit on the number of Nios II processors that can be used in a given design or a project. The Nios II processor IP license entitled a user to one year worth of support from Altera mySupport and feature updates. For new features, and Altera mySupport assistance users must renew their Nios II prcoessor IP licenses if it is not current within two releases of the ACDS version.

No. Synopsys® provides the Nios II DesignWare IP core, an ASIC optimized version of the Nios II Processor that can be used for ASIC migration as part of their DesignWare IP Suite. Contact Synopsys directly for more details.

The Nios II Embedded Design Suite (EDS) represents complete development tool suite for both the creation of Nios II processor-based microcontrollers as well as the programming of the target Nios II processor systems.

Multi-processor systems are one of the main benefits of the Nios II embedded processors. The only limitation on the number of processor cores is the resource limitation of the FPGA fabric.

The Avalon® interface specification is used for master and slave components to communicate with each other. For low latency, point-to-point interface, Avalon specifies a simple Avalon Streaming interface (Avalon-ST). For an interface where a processor's master interfaces with a peripheral slave, Avalon specifies an Avalon Memory Mapped interface (Avalon-MM).

System interconnect is logic that is used to connect master and slave components. This logic might be a bridge, a multiplexor, an arbitration controller. Qsys automatically generates system interconnect logic and connects master and slave ports efficiently allowsing multiple master ports to operate simultaneously, which dramatically boosts system performance.

 

The Avalon system interconnect is a custom-built interconnect that is automatically generated by Qsys.

The Nios II processor family provide the basic architectural elements found in most modern 32 bit processors, including:

 

32 bit instruction size

32 bit data and address paths

32 general-purpose registers

32 external interrupt sources

Configurable instruction cache

Configurable data cache

Common interface to up to 256 custom instructions

Common interface for the integration of custom peripherals

Custom instructions are user-added hardware blocks that augment the arithmetic logic unit (ALU) of a CPU. Nios II processors fully support the use of custom instructions, allowing you to fine-tune your system hardware to meet performance goals. You can create up to 256 custom instructions per Nios II processor core used in the system. Similar to native Nios II instructions, custom instruction logic can take values from up to two source registers and optionally write back a result to a destination register.

The Nios II prcoesspr software development tool automatically generates a customized C/C++ run-time environment tailored to the system hardware. The Nios II Embedded Design Suite also simplifies project setup by supplying several software templates which can be used as “starter” files in developing custom firmware solutions.

Altera provides a complete software debugging solution via the Nios II EDS that enables debug to occur via an instruction set simulator (ISS) or directly to system hardware. Direct debugging of a Nios II processor system in hardware is enabled through a hardware-assisted debug module. The debug module is rich in features and provides run control, memory examination and modification, hardware breakpoints, data triggers, and processor trace under IDE control.

Several top embedded software tools providers offer support for the Nios II family of processors, providing operating systems, middleware, software libraries, IDEs, debuggers, co-verification tools, and more. View the complete list of up-to-date embedded tools providers.

Documentation and Support


Find technical documentation, videos, and training courses for your Intel® Nios® II processor designs.