Andrew Lines

Intel Labs / Principal Engineer

Research Areas:

  • Algorithms, Architecture, Artificial Intelligence(AI), Circuits, Cognitive Computing

  • Computer Vision, Fabric Architecture, Graphics, HPC Systems, I / O

  • Interconnect, Low Power, Machine Learning, Memory Technology, Network & Communications Systems

  • Networking, Neuromorphic Computing, non-x86 Microarchitecture / ISA, Parallel Computing, Reinforcement Learning (RL)

  • SoC & IP Architecture and Design, Software Defined Infrastructure, x86 Instruction Set Architecture, x86 Microarchitecture



Andrew studied asynchronous circuit design as an undergrad and grad student at Caltech in the 90's. This involves the design of digital pipelined circuits that do not rely on a global clock to sequence operations, which has many interesting advantages over traditional synchronous design. In 2000, he co-founded Fulcrum Microsystems to commercialize this technology. After developing 4 commercial products for the network switching market, Fulcrum was acquired by Intel in 2011. Andrew helped deliver the FM10000 Ethernet switch while part of Intel's datacenter switching group. In 2013, he joined a project to port his Fulcrum TCAM design to Intel 14nm process. In 2015, Andrew and some other former Fulcrum employees transferred to Intel Labs to continue to develop asynchronous circuit technology, this time applied to neuromorphic computing. After 3 test chips, in 2018 we unveiled Loihi, a sophisticated 14nm silicon model of a biological brain, capable of simulating 128K neurons per chip and scaling to 100M neurons in large systems like Pohoiki Springs. Andrew designed the on-chip and off-chip interconnect for Loihi, and was a key architect for the neuron core. He also developed all the fundamental asynchronous building blocks.

Andrew is an expert in asynchronous circuit design using either of the popular design styles (QDI and BD). He is an inventor on over 15 patents, an author on over 10 papers, and architect of 17 fabricated chips. His specialties include asynchronous (and sometimes synchronous) design for SRAM, TCAM, crossbars, and CPUs. He also creates CAD tools, notably a SPICE simulator and automation scripts for physical design.