What's New in Intel® Quartus® Prime Software

Power and Performance

Intel® Agilex™ Device Support

The Intel® Quartus® Prime Pro Edition Software v21.1 supports the Intel® Agilex™ device family. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm process technology and 2nd generation Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance or up to 40% lower power.1

Compilation Strategies

The compiler in the Intel Quartus Prime Pro Edition Software is a fast, multi-faceted tool, allowing different compilation strategies that meet the designer’s needs. In addition to standard compilation, which can give you a baseline for performance, there are other compilation options available: 

  • Fast compile for small designs can be used to get quick compiles at the beginning of the development process when only a small portion of the design has been implemented.
  • High-effort compilation is used to make the compiler maximize its effort to get the best performance results out of a design.
  • Fast preservation compilations can be used with partitioned designs. Using a previously satisfactory compilation, fast preservation simplifies the logic of a preserved partition to only the interface between the partition boundary and the rest of the design. The use of fast preservation feature reduces the compile time required for the preserved partition and the overall compile time.
  • Back Annotation is used in conjunction with seed sweeping to take the best compilation from running different seeds. The best compilation from the run is then used as the starting point for additional seed sweeping after fixing in place the results of pin-placement, clocks, RAMS, digital signal processors (DSPs), or a combination of these. The results are typically higher Fmax with less variation in results. Additionally, a GUI for Back Annotation has been provided to make it even easier to use. Learn more.
  • Engineering Change Order (ECO) compilation is used when only minor changes are needed to an otherwise good compile. ECO compiles can provide a compilation speedup of 5X – 10X.2 It replaces the Rapid Recompile flow for post-fit Signal Tap changes with significant compilation speedup.

Additionally, there are many other parameters available to customize your compilation strategies to meet your specific requirements.

Power and Thermal Calculator

The Power and Thermal Calculator (PTC) supports Intel® Agilex™ and Intel® Stratix® 10 devices. For these devices, it replaces the older Early Power Estimator. It can be used inside the Intel Quartus Prime Pro Edition Software or as a stand-alone tool. The look and feel of the PTC has been improved allowing greater customization of the layout as well as tooltips to describe various parameters in the PTC. A new Thermals tab has been introduced for Intel Agilex devices, which allows you to do thermal analysis for the design and provides a method to obtain cooling solutions under various conditions.

Ease of Use

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enable faster design closure by reducing the number of design iterations required and speed every iteration with targeted sanity checks and guidance at every stage of the compilation process. View the video to learn more about the Design Assistant and Snapshot Viewer.

In the Intel Quartus Prime Pro Edition Software v21.1, 21 new rules have been added to the Design Assistant covering memory instantiation, clock domain crossing (CDC), and reset domain crossing (RDC). Many of the Design Assistant rules support cross probing to timing reports to make it easier to investigate paths. Additionally, a new rule classification for “fatal rule violation” has been added to stop the compilation if that rule is not followed. None of the Design Assistant rules are classified as “fatal”, but any of the rules can be changed to fatal classification by the designer.

New Reports

The Intel Quartus Prime Pro Edition Software continues to expand its rich set of compilation reports. In the v21.1 software release, the following new reports have been added:

  • Timing closure summary
  • Hierarchical reset
  • List clocks in path
  • CDC async

This new software version also includes improvements to the following existing reports:

  • Pipelining information
  • Logic depth
  • Neighbor paths
  • Timing

In addition to the new and improved reports, cross-probing between reports is supported in many of them. This expanding portfolio of reports enables you to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.

ECO Compilation

ECO Compilation provides a method to do small changes, such as changing a netlist connection, correcting a LUT logic error, or placing a node in a new location during the design verification stage. The ECO flow typically results in a lower compile time because only the specified ECO changes need to be compiled, leaving the rest of the design unchanged. Enhancements to this flow includes using the ECO compilation flow with the Signal Tap II Logic Analyzer, providing a GUI front-end for the ECO compilation (the fitter toolkit), and additional analysis tools to get the most out of the ECO compilation flow for design verification.

Platform Designer

Platform Designer has been enhanced to improve GUI performance in the Intel Quartus Prime Pro Edition Software. New features have been added to allow parameter support for HDL and Blackbox IP instantiations as well as the ability to pass parameters via register-transfer level (RTL). The Avalon® Multi-Master Pipeline Bridge now supports passing the writeresponsevalid signal back to the master component. Additionally, the Avalon® Streaming credit flow control, which provides higher performance through source flow control has been updated.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® 
Prime Design Software.

Informasi Produk dan Performa


Perbandingan ini didasarkan pada rangkaian Intel® Agilex™ FPGA dan SoC vs. Intel® Stratix® 10 FPGA menggunakan hasil simulasi dan dapat berubah. Dokumen ini berisi informasi tentang produk, layanan, dan/atau proses dalam pengembangan. Semua informasi yang diberikan di sini dapat berubah tanpa pemberitahuan sebelumnya. Untuk memperoleh perkiraan, jadwal, spesifikasi, dan panduan produk Intel terbaru, hubungi staf perwakilan Intel.
Fitur dan keunggulan teknologi Intel® bergantung pada konfigurasi sistem dan memerlukan perangkat keras yang didukung, perangkat lunak, atau aktivasi layanan. Pelajari lebih lanjut di intel.co.id, atau dari OEM atau peritel. Tidak ada sistem komputer yang sepenuhnya aman. Performa bervariasi berdasarkan penggunaan, konfigurasi, dan faktor lainnya. Pelajari lebih lanjut di www.Intel.com/PerformanceIndex.


Benchmark dilakukan terhadap rangkaian 28 desain di perangkat Intel® Stratix® 10 1S280 dengan sistem operasi Linux 64. Perbandingan ini dilakukan antara waktu kompilasi baseline dan waktu kompilasi ECO setelah perubahan netlist (8 - 2000 tergantung pada apa yang tersedia untuk perubahan ECO). Menguji performa komponen dokumen pada pengujian tertentu, dalam sistem yang spesifik. Setiap perbedaan pada perangkat keras, perangkat lunak, atau konfigurasi akan memengaruhi performa sebenarnya. Baca sumber informasi lainnya untuk mengevaluasi performa saat mempertimbangkan pembelian Anda. Untuk informasi umum tentang hasil performa dan benchmark, kunjungi http://www.intel.co.id/benchmarks.